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Mixed-Signal Verification Engineer – Hillsboro, OR – Hybrid
Responsibilities
- Develop top-down mixed signal verification strategies for state-of-the-art SoCs, ASICs, and IP blocks containing high speed digital circuits and sensitive analog/RF circuits.
- Development of automated test benches and simulation result evaluation tools for top down block verification.
- Perform actual verification work using the test benches and strategies developed.
- Development of tools for automated generation of verification reports and regression management.
- Integration and support of analog and digital designers developing Verilog-A, behavioral models into full system verification suites.
- Ensure validity and optimize performance of designer behavioral models. Ensure correct use of connect modules.
- Work with system architect to develop system tests, stimulating SoC from IC boundary, to ensure functionality with all types of data in all modes of operation.
- Develop automatic regression of verification suites using Cadence AMS Designer verification flow in Xcelium
Qualifications
- Master’s Degree in EE or ECE
- More than 2 years of experience with an Analog Design Flow (e.g. Cadence Virtuoso, Incisive/Xcelium, AMS-Designer, Verilog-AMS and Spectre).
- Experience with modelling languages: Verilog-A, Verilog-AMS, SystemVerilog/UVM.
- Experience with scripting languages such as Python, PERL, TCL, BASH/TCSH, etc. Matlab exposure beneficial.
- Knowledge creating mixed-signal self-checking test benches that run under automatic regression.
- Comfort working across both analog and digital design paradigms.
- Experience verifying ASICs utilizing power gating and multiple clock and power domains is desirable
- General understanding of analog circuits and ability to fit analog behavioral models.
- Self-driven, able to work independently while coordinating with analog and digital block designers
